1. Field of the Invention
The present invention relates to an ion implantation method which suppresses defect generation in very-large scale integration semiconductor devices.
2. Description of the Prior Art
The high density of current conventional semiconductor devices causes increased stress, which results in a condition in which defects can grow with extreme ease. Defect growth in a conventional semiconductor device is described below with reference to FIG. 14 using a MOS transistor as an example.
As shown in FIG. 14 (a), this device comprises a semiconductor substrate 1, MOS transistor gate electrode 2, an area of exposed oxide 3 for LDD (lightly doped drain) structure formation, a high concentration n+ area 5 formed by arsenic ion in the semiconductor substrate 1, and an amorphous layer 6 formed at the same time due to damage upon ion implantation in the semiconductor substrate 1. Reference number 4 indicates the arsenic ion beam used to form the source-drain area.
When the substrate is subjected to a heat treatment crystal regrowth occurs in the amorphous layer 6 and proceeds in two orthogonal directions at the corner thereof as shown in FIG. 14 (b): up from the bottom side of the substrate in direction 7, and in a horizontal direction 9. As a result, a void 10 where a crystal discontinuity exists is generated where the two directions of crystal regrowth collide, and a defect is thus formed. When a stress is applied to this defect area, the defect grows from the void 10. Tamura et al. have reported in the literature (Nuclear Instruments and Methods, B37/38, p. 329, 1989) on the formation of voids in this area.
Horiuchi et. al. [J. Appl. Phys., 65(6), Mar. 15, 1989, p.2238] proposes a method using a tapered mask. In this method, as shown in FIG. 6, there is formed a mask 201 of an oxide film with a tapered side surface. When an ion implantation is carried out in a vertical direction (an incident angle 0.degree. to 7.degree.) due to the tapered side surface of the mask 201, an edge or a corner portion of an amorphous layer 6 underlying the mask is formed tapered similarly to the taper of the mask. In other words, the side surface of the edge thereof has a dull angle. Thus, this method is an effective one for forming a dull edge of the amorphous layer to suppress defect generation.
However, in this method a pattern shift from a mask forming area is apt to be caused due to the formation of the taper and this is extremely inconvenient because the size of the device is miniaturized to one half of sub-micron order or less. In other words, this method is applicable only for devices having a relatively large size.
Further, since the reproducibility of taper etching is not so good, it is not applicable for super ULSI.